1. Field of the Invention
This invention is in the field of automated methods for analyzing the design of electrical circuits, such as integrated circuits, for compliance or noncompliance with various electronic circuit design rules.
2. Description of the Related Art
Although many of the areas related to the design of integrated circuits are well established and standardized, some areas are less well established, and less standardized. This is particularly true for situations where chip designers try to cope with various scenarios that are difficult to model by various standard electronic circuit simulation tools such as SPICE and other methods.
For example, consider the problems of designing an integrated circuit chip that has adequate protection against various Electrostatic Discharge (ESD) events. This is a problem that is difficult to model mathematically. This is because typical circuit devices, such as transistors, are typically driven at a few volts, and standard circuit modeling software is designed for this sort of voltage range. By contrast, ESD events can subject the same transistors to shocks of 10,000 volts or more, thus falling far beyond the ability of standard circuit modeling software to give accurate predictions.
As another example, consider the problem of designing a circuit that always has adequate digital driver strength as a function of signal loading. This problem is also difficult to model with standard software. The problem itself can occur when a driver originating in a first circuit power domain is not appropriately linked (e.g. there may or may not be a correct intermediate device such as a resistor) to a receiver circuit device that is located a second and different circuit power domain. Although a circuit design simulator may formally predict that a certain driver configuration is adequate in theory, due to the inability of the software to adequately simulate this part of the circuit, it may not be. Thus design engineers often find it to be prudent to increase driver strength by an empirical and often situation specific safety margin. Experienced circuit designers realize that such steps are needed to produce integrated circuit chips that adequately cope with real world events.
Other difficult to mathematically model problems include the problem of top-heavy drivers, combinations of input/output (IO) pairs that may be overly sensitive to electrical voltage problems, and the like. Here as well, design engineers often cope with these issues by coming up with various and often somewhat empirical circuit design rules.
These circuit design rules often are based on rules of thumb and a particular engineer's or organization's past experience with problems of that sort. Thus each circuit design group may have their own proprietary set of design best practices with regards to how a given integrated circuit should be designed and laid out. Some of these design best practices or electronic design rules include: keeping the physical separation between certain devices be kept at a certain minimum micron distance, adding ground spacers to help guard against possible failure modes, and adding various additional ESD clamp devices be added to certain Input/Output (IO) pads.
In practice, each design group may have one or more electronic design rule gurus, and each guru in turn may have their own set of electronic design rules. Thus integrated circuit chips designed by group “A” in response to input from design guru 1 may have to conform to a different set of electronic design rules (i.e. electronic rule checking or ERC) than the chips designed by group “B” in response to input from design guru 2.
Although some individual electronic design rules may be comparatively simple (e.g. if this situation exists, put in 1 ESD clamp for every “N” IO pads), modern integrated circuits are extremely complex. Thus the process of automatically checking a complex integrated circuit design netlist for compliance to such rules is not simple at all. Here because these design rules are be so variable (being very design guru, organization, and or situation dependent), prior art standardized electronic circuit design and validation software methods, which generally requires standardized rules to operate, often is inadequate for such situations.
Although prior art methods of automatically identifying specific topological patterns in integrated circuit design, such as Pikus et. al. (US publication 2010/0185994 assigned to Mentor Graphics Corporation) have been proposed, such prior art methods were rather narrowly oriented towards identifying particular physical topological structures in a circuit. Such methods are often unsuited for checking many types of electronic design rules.
Other prior art in the field includes Arayama (U.S. Pat. No. 8,000,951, assigned to Fujitsu Limited). Arayama's methods provide templates for finding specific circuit subsets (or subgraphs) such as inverters, flip-flops, or feedback loops, but otherwise are also unsuited for checking many types of electronic design rules.
In principle, because the chip design itself is present in computer readable form (e.g. a computer readable netlist), and because the various local electronic design rules can be expressed logically (e.g. by a large table of contingencies and rules, or procedural decision making), the problem of electronic rule checking is a software problem. In practice however, using brute force software methods to implement such variable and guru dependent rules is very problematic, because the burden of writing large amounts of customized code for each design rule situation and each guru is just too great to be manageable. Certainly any given chip designer (electronic circuit engineer), who needs to know if a particular integrated circuit design is complying with their local set of electronic design rules will generally lack both the skills and time needed to write the large amounts of customized code that prior art methods would require to be used for these situations.
Thus at present, the field is in an unsatisfactory state, because the process of troubleshooting a particular circuit design, at least according to non-standardized electronic design rules, usually requires more skills and time than design engineers, using prior art circuit design and debugging software, can provide.